This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-265205, filed Sep. 20, 1999, the entire contents of which are incorporated herein by reference.
The present invention relates to a non-volatile semiconductor memory device and a manufacturing method thereof. Further, the present invention relates to the shape of end portions of a gate electrode formed in each of element regions insulated and isolated by embedded isolation regions. The present invention is applicable to a non-volatile semiconductor memory device of a batch-erasure type such as a NOR-type flash EEPROM or the like, and a memory-mounting logic integrated circuit.
In a semiconductor memory device having element regions insulated and isolated by embedded isolation regions, e.g., in a flash EEPROM, the film thickness of the gate oxide film in MOS transistors formed in a cell array region and that of MOS transistors formed in a peripheral transistor region are different from each other in order to optimize respectively performances of the MOS transistors formed in those regions.
In manufacture of a semiconductor memory device having element regions which are insulated and isolated by embedded isolation regions as described above, gate oxide films having different film thicknesses are formed. For example, gate oxide films of two different film thicknesses are formed. In this case, generally, a substrate is firstly-oxidized over its entire surface thereby to form a gate oxide film having a first film thickness, and the first gate oxide film is next remove partially in the region where a gate oxide film having a second film thickness is formed. Further, masking is carried out so that oxidation seeds might not be provided in the region where the first gate oxide film should remain formed. Thereafter, the second gate oxide film is formed.
In consideration of the relationship with a step of forming an isolation region, there may be various methods for forming gate oxide films having different film thicknesses as described above. For example, a flash EEPROM adopts a method in which a part of gate oxide films is formed before the step of forming isolation regions, and the other part of the gate oxide films is formed after the step of forming the isolation regions forming step.
Meanwhile, in a non-volatile semiconductor memory device having a two-layer gate structure (stacked gate) including a control gate and a floating gate, as represented by a flash EEPROM, there is a case that isolation is achieved by Shallow Trench Isolation (STI). If the floating gate falls into the isolation region at an edge of an active area which contacts with a STI region, electric field concentration on this edge causes variants of the memory cell characteristics and particularly variants of the tunnel current amount used for writing and erasure.
To reduce the variants of the tunnel current amount, a method has been taken in which a STI region is formed so that floating gates and element regions are formed with the positions of their end portions self-aligned with each other, after a tunnel oxide film for memory cells and a polysilicon film for floating gates are formed.
Also, the following method is adopted to maintain a sufficient capacitive coupling between a control gate and a floating gate. That is, the floating gate is formed of first and second polysilicon films. The second polysilicon film is formed on the first polysilicon film so that the second polysilicon film is directly connected with the first polysilicon film. Further, the second polysilicon film is extended over the STI regions.
These techniques are disclosed in, for example, K. Shimizu et al., xe2x80x9cA Novel High-Density 5F2 NAND STI Cell Technology Suitable for 256 Mbit and 1 Gbit Flash Memoriesxe2x80x9d international ELECTRON DEVICES meeting 1997, WASHINGTON, D.C. Dec. 7-10, 1997, IEDM Technical Digest Paper pp 271-274.
Next, explanation will be made of steps of manufacturing the non-volatile memory, disclosed in the above reference.
This method is adopted to a case of a flash memory having a memory cell part and a peripheral circuit part. FIGS. 1A to 1D shows steps of manufacturing the memory cell part, and FIGS. 2A and 2B shows steps of manufacturing the peripheral circuit part.
Note that the memory cell part has an array of stacked-gate-type cell transistors each having a control gate and a floating gate. In the stacked-gate-type cell transistor, the floating gate is comprised of two polysilicon films, and trenches for isolation are formed to be self-aligned with a polysilicon film as a first layer. A polysilicon film as a second layer is formed above the polysilicon film as the first layer.
At first, as shown in FIG. 1A, a tunnel oxide film (a tunnel oxide film for memory cells) 32 having a film thickness of 10 nm is formed on a silicon substrate 31. A first polysilicon film 33 to form part of floating gates is formed on the tunnel oxide film. Next, as shown in FIG. 1B, a first polysilicon film 33, a tunnel oxide film 32, and a silicon substrate 31 are etched with use of a predetermined etching mask, thereby forming a plurality of grooves 34 in the silicon substrate 31. These grooves 34 form STI for isolation. Also, the silicon substrate 31 is separated into a plurality of element regions.
Next, as shown in FIG. 1C, the grooves 34 are filled with an insulating film 35 for isolation. Further, a second polysilicon film 36 to form part of the floating gates is formed. Subsequently, a control gate 38 is formed with a gate insulating film 37 inserted thereunder, as shown in FIG. 1D.
Meanwhile, with respect to the peripheral circuit part, the memory cell part is covered and protected by a photoresist not shown, in a stage in which the first and second polysilicon films 33 and 36 are formed, as shown in FIG. 2A. Further, as shown in FIG. 2B, the second polysilicon film 36 and the first polysilicon film 33 are removed from the peripheral circuit part. Further, the tunnel oxide film 32 is removed therefrom. Thereafter, a polysilicon film for gate oxidation and gate electrodes is deposited again, thereby to form a gate oxide film 37 and gate electrodes 38 are formed.
At this time, if the gate electrodes 38 are formed to fall in the STI regions at edges of element regions, parasitic transistors are created among MOS transistors.
FIG. 3 is a cross-sectional view in which an edge part 3 of an element region surrounded by a circle mark in FIG. 2B is picked up and enlarged.
If the gate electrode 38 falls into the STI region a t edges of an element region, a parasitic transistor appears in the region B surrounded by a circle mark in the figure. If the parasitic transistor operates, a kink occurs in the subthreshold characteristic, thereby involving increase of the stand-by current. In particular, if the corner parts of the element region are not rounded, the field-effect concentration effect is increased so that the kink characteristic is emphasized.
To prevent this, it is advantageous to carry out a so-called rounding oxidation step of rounding the corner parts of the edge part A of the element region and of creating birds-beaks in the tunnel oxide film 32, before STI regions are filled with the insulating film 35 during formation of STI, as shown in FIG. 4. By optimizing the thickness of the oxide film in the rounding oxidation step, the extent to which the gate electrodes fall in the STI region can be restricted, for example, as shown in FIG. 5.
The rounding oxidation step descried above has been proposed in the U.S. patent Ser. No. 09/527,870 xe2x80x9cSemiconductor Device and manufacturing Method Thereofxe2x80x9d. By the technique e proposed therein, it is possible to restrict the leakage current and the current consumption within a region where the gate voltage of the peripheral circuit transistors is low in a flash EEPROM which adopts the STI isolation structure. Accordingly, the subthreshold current characteristic is rendered sequential in relation to the gate voltage, and the operation is stabled in the region where the gate voltage is low, so that the yield of products can be improved.
However, even in the method for manufacturing a semiconductor device according to the above proposal, the gate electrode 38 has a shape slightly caved into a part where the insulating film 35 isolation is etched, in the step of removing the tunnel oxide film 32 in the peripheral transistor region.
Thus, if the gate electrodes of MOS transistors fall in the side of the STI regions at edge portions of isolation regions in the peripheral transistor region, the electric field is concentrated on the edge portions of isolation regions. Consequently, the threshold voltage of the MOS transistors is lowered, and the subthreshold characteristic causes a kink, resulting in the problem of increase of the current consumption.
Meanwhile, a problem may be caused in the memory cell part if the rounding oxidation step described above is carried out in manufacture of a non-volatile semiconductor memory device including an array of memory cell transistors as follows. That is, in this area, floating gates of stacked-gate-type memory cell transistors are each comprised of two layers of polysilicon films, wherein trenches for isolation are formed to be self-aligned with a polysilicon film as the first layer, and a polysilicon film as the second layer is formed above the polysilicon film as the first layer.
Specifically, the first polysilicon film 33 shown in FIG. 1D is oxidized during the rounding oxidation, so the shape of this film is rounded and an oxide film 39 is further formed above the first polysilicon film 33. This state is shown in FIG. 6 and FIG. 7 which enlarges the region 7 surrounded by a circle mark in FIG. 6.
If an oxide film 39 is formed above the rounded parts of the first polysilicon film 33 by carrying out the rounding oxidation step as described above, it is necessary to remove a constant amount of the oxide film from the upper part and side surfaces of the first polysilicon film 33, before forming the second polysilicon film 36. Otherwise, the oxide film 39 existing above the rounded parts of the first polysilicon film 33 may function as a mask when vertical etching is performed on the stacked gates of the memory cells in a later step. Consequently, the first polysilicon film 33 may remain like a filament, so the floating gates (made of the first polysilicon film 33) may be short-circuited between adjacent memory cells.
In FIG. 7, the part 33B of the side surface of the first polysilicon film 33 indicates the portion where an etching residue appears when vertical etching is carried out. The parts where the etching residues appear may continue to each other between a plurality of adjacent memory cells in the depth direction in the figure. As a result, short-circuiting is caused between the floating gates described above.
The present invention therefore has an object of providing a non-volatile semiconductor memory device and a manufacturing method thereof, which are capable of restricting increase of the current consumption by minimizing falls of gate electrodes of peripheral circuit transistors formed after forming an embedded isolation film, into isolation grooves at end portions of isolation regions.
According to the present invention, there is provided a non-volatile semiconductor memory device comprising: a semiconductor substrate; a plurality of embedded isolation regions each having a groove formed on a surface of the semiconductor substrate, and constructed in a structure that the grooves are internally filled with an insulating film; a plurality of element regions formed by separating the semiconductor substrate by the plurality of embedded isolation regions; a plurality of memory cell transistors respectively formed in a part of the plurality of element regions; and a plurality of peripheral circuit transistors respectively formed in another part of the plurality of element regions, each of the peripheral circuit transistors having a gate insulating film and a gate electrode formed on the gate insulating film, and the gate electrodes being formed to be positioned above an uppermost portion of the grooves of the embedded isolation regions.
Further, according to the present invention, there is provided a non-volatile semiconductor memory device comprising: a semiconductor substrate; a plurality of embedded isolation regions each having a groove formed on a surface of the semiconductor substrate, and constructed in a structure that the grooves are internally filled with an insulating film; a plurality of element regions formed by separating the semiconductor substrate by the plurality of embedded isolation regions; a plurality of memory cell transistors respectively formed in a part of the plurality of element regions, each of the memory cell transistors including a first gate insulating film formed on the semiconductor substrate, a floating gate electrode formed of first and second conductive films layered on the first gate insulating film, a second gate insulating film formed on the floating gate electrode, and a control gate electrode made of a third conductive film formed on the second gate insulating film; and a plurality of peripheral circuit transistors respectively formed in another part of the plurality of element regions, each of the peripheral circuit transistors including a third gate insulating film formed on the semiconductor substrate, and a gate electrode formed on the third gate insulating film, wherein the second conductive films at interfaces of the embedded isolation regions to the grooves are formed to be positioned below an uppermost portion of the grooves, and the gate electrodes are formed to be positioned above the grooves of the embedded isolation regions.
Also, according to the present invention, there is provided a method for manufacturing a non-volatile semiconductor memory device, comprising: a step of forming a layered film including a first gate insulating film, a first polysilicon film, a first silicon nitride film, and a first silicon oxide film layered sequentially on a silicon semiconductor substrate; a step of making the layered film remain in a predetermined pattern shape; a step of forming a plurality of isolation grooves by sequentially removing the first polysilicon film, the first gate insulating film, and the silicon semiconductor substrate, with the layered film used as a mask, thereby to form a plurality of element regions on the silicon semiconductor substrate; a step of forming a first photoresist so as to cover a cell array region of the silicon semiconductor substrate; a first pull-back processing step of pulling back side surfaces of the first polysilicon film in peripheral circuit transistor region, inwards by a predetermined amount from side surfaces of the isolation groove of the silicon semiconductor substrate, by isotropic etching; a step of removing the first photoresist; a second pull-back processing step of processing an entire surface by isotropic etching, thereby to pull back side surfaces of each of the first silicon nitride film inwards by a predetermined amount from the side surfaces of the isolation grooves of the silicon semiconductor substrate; an oxidation step of performing oxidation thereby to round upper corner portions of each of the element regions and to form an oxide film on exposed surfaces of the silicon semiconductor substrate and the first polysilicon film; a step of depositing an isolation insulating film on an entire surface including insides of the isolation grooves; a flattening step of performing polishing thereby to remove the isolation insulating film, the first silicon oxide film, and the first silicon nitride film such that the first silicon nitride film partially remains; a step of removing the first silicon nitride film remaining after the polishing; a step of forming a second photoresist so as to cover the peripheral circuit transistor region; a step of removing the isolation insulating film on the first polysilicon film, by isotropic etching; a step of removing the second photoresist; a step of forming a second polysilicon film on an entire surface; a step of patterning the second polysilicon film thereby to separate the second polysilicon film for respective pieces of the first polysilicon film on the cell array region; a step of forming a second gate-insulating film on an entire surface; a step of removing the second gate insulating film, the second polysilicon film, the first polysilicon-film and the first gate insulating film thereunder on the peripheral circuit transistor region; a step of forming a third gate insulating film on each of the element regions in the peripheral circuit transistor region; and a step of forming a third polysilicon film on an entire surface.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.